Architecture 2.0

Abstract: The genius of FORTRAN, introduced in 1957, was not just that it was the first high-level language, but that it made hardware disappear. The same FORTRAN program could run on an IBM System/360, a DEC PDP-8, a CDC 6600, or even a Cray-1 with enough performance that most programmers never had to touch assembly or write architecture-specific code.

Over time, as hardware and software grew more complex, compilers quietly lost the ability to maintain this abstraction. Multicores, complex vector instructions, and specialized accelerators have all pushed more of the performance burden back onto the programmer. Today we have, in many ways, come a full circle. For example, getting peak performance from NVIDIA's V100, A100, H100, and B100 families often requires different, architecture-specific CUDA kernels and, on the latest parts, even hand-written PTX assembly to fully exploit tensor cores and the Tensor Memory Accelerator. To the best of our knowledge, the Apple/Arm SME accelerator does not even have a high-level compiler, and most high-performance code must be written using intrinsics or assembly.

This raises a fundamental question: can the next generation of compilers restore the original promise of the high-level programming languages—hiding architectural complexity while still delivering near-peak performance?

In this talk, I will argue that the answer is yes, and I will outline a path forward for us to modernize compilers—both to make them far more effective on today's architectures and to radically simplify how we build them—by creating proper abstractions and leveraging machine learning and other modern techniques.

Bio: Saman Amarasinghe is the Thomas and Gerd Perkins Professor in the Department of Electrical Engineering and Computer Science at MIT and leads the Commit compiler research group in MIT's Computer Science & Artificial Intelligence Laboratory (CSAIL). Born in Sri Lanka and schooled at Royal College, Colombo, he is a graduate of Cornell University and earned his Master's and PhD degrees from Stanford University. He was elected as an ACM Fellow in 2019.

Abstract: In the coming years, agentic AI is poised to take HW/SW co-design to the next level. This talk will cover several aspects of my group's work on AI-driven co-design, including successes in automated architectural discovery and our hot-off-the-presses open-source framework for AI-driven hardware/software co-design called CHIA (https://chialoops.ai).

We will begin by discussing ArchAgent (OpenReview, Nov. 2025), the first agentic, evolutionary, generative AI system that can automatically design new hardware mechanisms (i.e., not just parameter tuning). ArchAgent achieves SoTA solutions to established problems (e.g., cache replacement competitions on SPEC) without human intervention. In addition to a technical deep dive, we will cover the key challenges/lessons learned and the broad implications of systems like ArchAgent on the field of computer architecture.

On the way to addressing these challenges, we will review the past decade of advances in agile hardware/software co-design that have been driven by the application of software engineering principles to hardware design. These include concepts like building flexible hardware generators (Chipyard RISC-V SoC Framework), cost-efficient cloud scaling and automatic design transformation (FireSim FPGA-accelerated HW Simulator), and process/tool portability and modularity (Hammer ASIC Flow).

Given our learnings from both of these domains, we will introduce the brand new (released yesterday!) CHIA project (https://chialoops.ai, OpenReview, June 2026). CHIA is an open-source hardware/software co-design framework for agile and principled research on the application of AI to co-design. CHIA treats the productive construction and scalable deployment of the co-design flow itself as a first-class objective. In CHIA, agentic AI-driven hardware and software design flows are expressed as CHIA loops: directed cyclic graphs whose nodes execute various system-on-chip design tools, microarchitectural simulators, software build systems, AI models, evolutionary coding agents, and more. The CHIA library provides node implementations for many popular tools, including Chipyard, gem5, ChampSim, FireSim, Hammer (thus several commercial ASIC CAD tools), Vivado, AlphaEvolve, AdaEvolve, and many others. We will discuss several case studies to show CHIA's capabilities and are excited to see what the community does with CHIA!

Bio: Sagar Karandikar is an Assistant Professor of Electrical Engineering and Computer Sciences (EECS) at UC Berkeley and the Jean and Hing Wong Foundation Faculty Fellow at UC Berkeley. His group works on areas including agile, open-source, AI/ML-infused hardware/software co-design methodologies, hardware accelerator and server system-on-chip design, and full-stack (HW + SW) system optimization and profiling. His work has received several recognitions, including an ISCA@50 25-year Retrospective selection, an IEEE Micro Top Picks selection, an IEEE Micro Top Picks honorable mention, a MICRO Distinguished Artifact Award, an ISCA Distinguished Artifact Award, and more. His work, including the open Chipyard and FireSim projects, is also widely used in the community. For example, FireSim has been used (not only cited) in over 85 peer-reviewed publications from first authors at over 35 institutions, in the development of commercially available chips, and as a standard host platform for DARPA/IARPA programs. Other recognitions he has received include: the 2025 ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award, a Google ML and Systems Junior Faculty Award, the David J. Sakrison Memorial Prize, and selection as a DARPA Riser. More info: https://sagark.org

Abstract: The AI datacenter stack runs on hardware-software contracts written for a world where humans wrote all the code and designed all the hardware, but both are now changing. With datacenters projected to draw over 1,000 TWh annually and the next efficiency leap demanding two orders of magnitude of improvement, renegotiating the hardware-software contract is no longer optional.

This talk turns head-on to agentic co-design: from embedding learning inside low-level mechanisms with works like LVM, to systems like LithOS that rethink the OS contract over GPUs for AI and agentic serving, to full agentic co-design with our progress on Agentic Architect, a framework for LLM-driven architecture design space exploration and optimization.

Architects are uniquely positioned to close the agentic loop. The benchmarks, simulators, and metrics are already here. In the last part of the talk I'll cover a few of the things that are still missing. This is a call to action for the community best positioned to define the next generation of the system stack: our community.

Bio: Dimitrios Skarlatos is an assistant professor in the Computer Science Department at Carnegie Mellon University. His research bridges computer architecture and operating systems with a focus on AI datacenter efficiency, privacy, and scalability. His work has been deployed in production datacenters and upstreamed into the Linux kernel. He has received the IEEE CS TCCA Young Computer Architect Award, the NSF CAREER Award, the Intel Rising Star Award and the Intel Outstanding Researcher award, a Linux Foundation Faculty Award, an ISCA Best Paper Award, two ASPLOS Best Paper Awards, a CACM Research Highlight, four IEEE MICRO Top Picks, the joint ACM SIGARCH & IEEE CS TCCA Outstanding Dissertation Award, and over a dozen industry faculty awards from Amazon, AMD, Intel, Meta, Oracle, and VMware. His recent work led to the founding of LithosAI.

Abstract: Design space exploration (DSE) is central to computer architecture, helping designers navigate large spaces of algorithmic, architectural, and mapping choices to optimize performance, power, and area. Yet current DSE flows still require substantial manual effort and remain largely bounded by human-defined abstractions, performance models, and search spaces.

As the field approaches its "AlphaZero moment", this talk looks beyond using AI to accelerate search within a fixed design space. The larger opportunity is to build AI architects: agentic systems that automate under-formalized design tasks, perform knowledge-guided search, and expand exploration beyond choices explicitly specified by humans.

To ground this vision, we revisit existing DSE workflows to identify where manual effort remains and where generative AI can meaningfully extend automation. As one example, we present SOLAR, an agentic framework that interprets algorithms and translates them into performance-model-ready representations, showing how AI architects can support the less structured stages of DSE.

Finally, we connect AI for architecture to the broader AI-for-X landscape, especially AI for coding. We discuss transferable lessons from coding agents while highlighting challenges unique to hardware architecture. We conclude with a call for new benchmarks, methodologies, and infrastructure to build creative yet trustworthy AI architects for scalable DSE and to accelerate hardware innovation.

Bio: Qijing Jenny Huang is a Senior Research Scientist at NVIDIA. Her research focuses on AI for computer architecture exploration, with the goal of advancing full-stack automation of architecture design. A central theme of her work is deriving speed-of-light performance limits for emerging workloads and technologies, and developing automatic methods to close the gap between those limits and practical systems. Her broader research spans algorithm-hardware co-design for deep learning, agile design methodologies, and scheduling optimization. Her work has been recognized by IEEE Micro Top Picks, an ISCA Best Paper nomination, and EECS Rising Stars. She received her Ph.D. in Computer Science from UC Berkeley.